cv
Basics
Name | Kyeongmin Cho (조경민) |
Label | Software Engineer |
kyeongmin.cho@rebellions.ai | |
Url | https://kyeongmincho.com |
Education
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2019.09 - 2024.08 Daejeon, Korea
Korea Advanced Institute of Science and Technology (KAIST)
Ph.D. in Computer Science
- Advisor: Jeehoon Kang
- Dissertation: Principles of Byte-Addressable Persistency
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2013.03 - 2019.08 Incheon, Korea
Inha University
B.S. in Computer Science and Engineering
B.A. in Philosophy (double major)
Work
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2024.09 - Present Seongnam, Korea
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2016.07 - 2017.08 Seoul, Korea
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2015.06 - 2016.06 Seoul, Korea
Publications
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OOPSLA 2024 Quantum Probabilistic Model Checking for Time-Bounded Properties
Seungmin Jeon, Kyeongmin Cho, Changu Kang, Janggun Lee, Hakjoo Oh, Jeehoon Kang
Object-oriented Programming, Systems, Languages, and Applications
Abstract
Probabilistic model checking (PMC) is a verification technique for analyzing the properties of probabilistic systems. However, existing techniques face challenges in verifying large systems with high accuracy. PMC struggles with state explosion, where the number of states grows exponentially with the size of the system, making large system verification infeasible. While statistical model checking (SMC) avoids PMC’s state explosion problem by using a simulation approach, it suffers from runtime explosion, requiring numerous samples for high accuracy.
To address these limitations in verifying large systems with high accuracy, we present quantum probabilistic model checking (QPMC), the first method leveraging quantum computing for PMC with respect to time-bounded properties. QPMC addresses state explosion by encoding PMC problems into quantum circuits that superpose states within qubits. Additionally, QPMC resolves runtime explosion through Quantum Amplitude Estimation, efficiently estimating the probabilities of specified properties. We prove that QPMC correctly solves PMC problems and achieves a quadratic speedup in time complexity compared to SMC.
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PLDI 2023 Memento: A Framework for Detectable Recoverability in Persistent Memory
Kyeongmin Cho, Seungmin Jeon, Azalea Raad, Jeehoon Kang
Programming Language Design and Implementation
Abstract
Persistent memory (PM) is an emerging class of storage technology that combines the performance of DRAM with the durability of SSD, offering the best of both worlds. This had led to a surge of research on persistent objects in PM. Among such persistent objects, concurrent data structures (DSs) are particularly interesting thanks to their performance and scalability. One of the most widely used correctness criteria for persistent concurrent DSs is detectable recoverability, ensuring both thread safety (for correctness in non-crashing concurrent executions) and crash consistency (for correctness in crashing executions). However, the existing approaches to designing detectably recoverable concurrent DSs are either limited to simple algorithms or suffer from high runtime overheads.
We present Memento: a general and high-performance programming framework for detectably recoverable concurrent DSs in PM. To ensure general applicability to various DSs, Memento supports primitive operations such as checkpoint and compare-and-swap and their composition with control constructs. To ensure high performance, Memento employs a timestamp-based recovery strategy that requires fewer writes and flushes to PM than the existing approaches. We formally prove that Memento ensures detectable recoverability in the presence of crashes. To showcase Memento, we implement a lock-free stack, list, queue, and hash table, and a combining queue that detectably recovers from random crashes in stress tests and performs comparably to existing hand-tuned persistent DSs with and without detectable recoverability.
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PLDI 2021 Revamping Hardware Persistency Models: View-Based and Axiomatic Persistency Models for Intel-x86 and Armv8
Kyeongmin Cho, Sung-Hwan Lee, Azalea Raad, Jeehoon Kang
Programming Language Design and Implementation
Abstract
Non-volatile memory (NVM) is a cutting-edge storage technology that promises the performance of DRAM with the durability of SSD. Recent work has proposed several persistency models for mainstream architectures such as Intel-x86 and Armv8, describing the order in which writes are propagated to NVM. However, these models have several limitations; most notably, they either lack operational models or do not support persistent synchronization patterns.
We close this gap by revamping the existing persistency models. First, inspired by the recent work on promising semantics, we propose a unified operational style for describing persistency using views, and develop view-based operational persistency models for Intel-x86 and Armv8, thus presenting the first operational model for Armv8 persistency. Next, we propose a unified axiomatic style for describing hardware persistency, allowing us to recast and repair the existing axiomatic models of Intel-x86 and Armv8 persistency. We prove that our axiomatic models are equivalent to the authoritative semantics reviewed by Intel and Arm engineers. We further prove that each axiomatic hardware persistency model is equivalent to its operational counterpart. Finally, we develop a persistent model checking algorithm and tool, and use it to verify several representative examples.
Awards
- 2021.12.05
NAVER Ph.D. Fellowship Award
NAVER Corp.
- 2018.12.27
Best Award (1st place)
Computer Science Capstone Design Competition, Inha University
Project: A Framework for Fuzzing Android Applications
- 2014.11.08
Bronze Award (14th place)
ACM International Collegiate Programming Contest (ICPC) Regional Contest, ACM
- 2014.02.21
Kiwoom Securities Financial Scholarship
Kiwoom Securities Corp.
Certificates
정보처리기사 | ||
한국산업인력공단 | 2020-08-28 |
日本語能力試験 (JLPT) 1級 | ||
Japan Foundation | 2009-08-28 |
Languages
Korean | |
Native speaker |
English | |
Professional working proficiency |
Japanese | |
Professional working proficiency |